一種用于激光告警機的圖像采集與處理系統設計-AET-電子技術應用

一種用于激光告警機的圖像采集與處理系統設計

微計算機信息

摘要： 一種用于激光告警機的圖像采集與處理系統設計1引言激光告警機是被動光電偵查設備，其功能是探測目標激...

關鍵詞： FPGA 圖像采集激光告警機 IP 嵌入式 PLD CPLD SOC 數字信號處理消費電子

Abstract：

Key words :

1引言

激光告警機" title="激光告警機">激光告警機是被動光電偵查設備，其功能是探測目標激光信號的性質，如波長、方位等，本系統能夠完成探測并提取激光波長信息的功能。在激光波長測量系統中，激光信號從CCD相機輸出到信號處理器的時間和處理器的處理時間是能否做到實時監測激光波長的兩大關鍵，即使采用高速單片機也限于它的串行處理模式和較長的取指時間，無法滿足實時測量的目的，因此為實現在幾毫秒內就對目標激光信號的波長做出反應只能寄希望于高性能的DSP器件或FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" 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title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA" title="FPGA">FPGA器件了。告警系統中，相機的接口為器件的選擇則也提出要求：采集器件要支持LVDS 電平，否則要加入電平轉換芯片，這勢必會帶來數據傳輸的延時；此外應用FFT進行數據處理時，由于FFT在算法上具有可重復性和可并行處理的特點，為實現實時性處理，要求選擇具有并行處理功能的處理器。在設計中選用Xilinx公司的Sp3系列FPGA作為控制、處理器，將FPGA用在本系統中的好處有： (1)高密度FPGA可在一塊片子上實現多個子模塊，有效減小激光告警接收機的體積；(2)FPGA具有成熟的時鐘管理體系，和精確的時鐘控制體系，能夠實現采集與處理的無縫連接，從而提高系統可靠性；(3)FPGA支持多種信號標準，尤其在告警系統中FPGA可將接口設置為LVDS型，使得FPGA與相機的通信更加直接，避免了以往采用電平轉換芯片的相關工作；（4）FPGA具有并行處理功能，能夠實現流水作業，可減少信號處理時進行FFT運算的時間。
2原理概述
　相機將探測到的激光信號通過Cameralink接口方式傳遞給FPGA，FPGA控制時序產生來完成以下工作：向CCD輸入時鐘信號；通過觸發端設置 CCD積分時間；倍頻相機的STROBE信號實現接收數據的串并轉換；將并行數據在讀使能的控制下從FIFO中轉入塊RAM。為提高激光告警機的響應時間該系統充分利用FPGA可流水作業這一功能，在數據接收端提供兩個1024個單元的數據存儲器交替工作，通過在軟件上設立標志位來實現對存儲區間進行切換。在數據存儲和數據處理時，當FPGA用1 區進行采集數據的第i幀時，同時2 區進行第i-1幀數據的處理，當兩者同時結束后，接著又用2 區進行第i+1幀數據的采集, 同時1 區進行第i 幀數據的處理, 這樣交替工作，形成流水線作業。由于相機采集速率和塊RAM寫入時間的不同，在FPGA內部采用IP" title="IP">IP 核生成兩個FIFO為兩路數據的接收實現緩沖來取得同步。塊RAM的寫入、讀出時序和地址發生器由VHDL語言編寫完成。數據的處理通過在時鐘的同步下逐一讀取RAM中的數據，采用十級流水基-2算法實現1024點的快速傅里葉變換，得出輸入激光信號的頻譜特性。激光告警機的采集和處理系統框圖如圖1所示。

3系統設計
整個系統由兩部分構成：數據采集模塊，數據處理模塊。
3.1 CCD相機數據采集模塊
在設計中采用ATMEl公司的AViiVA M2 CL相機，該相機采用Cameralink接口，Cameralink技術的核心是美國NS(National Semiconductor)提出的一種高速數據傳輸方法—Channel Link技術，該技術主要用于數字圖像數據的高速傳輸，采用LVDS信號模式，LVDS低電壓擺幅差分模式具有高速傳輸數據時交叉干擾小、EMI 干擾小等優點，最高傳輸率可達2.38Gb/s。該相機的接口定義為：四對LVDS線，用來做FPGA對相機的控制；兩對LVDS線，用于相機和FPGA 之間的通信，速度可達9600波特率；四對LVDS線，用于輸出數據和數據的位同步、幀同步信號。選用XC3S400型的FPGA，它具有豐富的接口標準尤其是支持LVDS 信號標準，可與Cameralink接口的相機直接連接。相機工作方式的設置由FPGA基于RS-232協議串行通信來實現，采用全雙工，沒有握手信號的異步串行方式，波特率固定在9600Hz，每幀數據由一個起始位，8個數據位，一個停止位組成。相機的積分時間和輸出增益都是可以根據需要設置為不同的值。對于相機工作的觸發方式由FPGA外部觸發，做到FPGA與相機共用同一個全局時鐘。

　在數據的采集過程中，數據傳送的同步信號由 STROBE引腳產生，當數據在一個數據區存滿時，通過LVAL引腳通知FPGA 轉到另一數據存儲區。圖2 給出了數據采集的時序圖。其中CLK_IN是由FPGA的內核數字時鐘管理模塊DCM 來實現倍頻得到。在時鐘控制和管理方面DCM比DLL功能更強大,使用更靈活。DCM的主要功能包括消除時鐘時延、頻率綜合和時鐘相位的調整。在本設計中對輸入時鐘STROBE作8倍頻處理，以實現數據一轉八串并轉換的鎖存輸出。

高速采集程序的設計主要有接口匹配、采集狀態機和數據存儲三部分。在接口匹配中由于LVDS 的輸入與輸出都是內匹配的,所以LVDS 間可直接連接。在FPGA 內,需對差分輸入時鐘緩沖器(IBUFDS)、差分輸入的全局時鐘緩沖器(IBUFGDS)和差分輸出時鐘緩沖器(OBUFDS) 例化。
FPGA 的部分代碼如下:
component IBUFDS - - 差分輸入時鐘緩沖器( IBUFDS)
port (O : out STD_ULOGIC;
I : in STD_ULOGIC;
IB : in STD_ULOGIC) ;
end component ;
IBUFDS_INSTANCE_NAME: IBUFDS
port map (O=>user_O,I=> user_I,IB =>user_IB) ;
3.2數據處理模塊
Spartan3系列FPGA有豐富的乘法器資源，在不使用任何優化算法的情況下每一個蝶形運算需要4個實數乘法器，因此在FPGA中每個蝶形運算可以用 4個乘法器在一個時鐘周期內完成。豐富的RAM資源便于實現數據的流水操作，即對于輸入、輸出數據以及中間變量可以開辟不同的存儲區，例如當計算第i組數據時，第i-1組計算結果正在輸出，第i+1組數據正在輸入。
由于在FFT運算中必然產生復數，因此為使計算方便，在設計之初就將FFT變換器的數據輸入口分為實數和虛數。1024點復數FFT運算，按照基-2頻率抽取運算分成10級，每級包括1個雙端RAM，1個地址發生器，一個ROM用于存儲旋轉因子表，1個蝶形運算單元,2個選擇緩沖單元。為了簡化地址單元電路,將復數數據的實部虛部組合成一個數據存儲在RAM中。由于使用雙口RAM ,當一個存儲單元中的數據讀出做運算時,該存儲單元就能夠存儲上一級來的數據,因此這種結構的FFT 可以進行流水線操作,能夠對信號樣本進行實時連續的運算。選擇緩沖器的用途是拉齊數據,將RAM 輸出的2個復數數據拆成4個實數數據輸入到蝶形運算單元,完成蝶形運算后的數據進入選擇緩沖器組合成2個復數數據輸出。

     可見復數乘法需要的實數乘法由原來的4個變為3個，式中因子可作為常數存入ROM，這樣復數乘法只需3個實數乘法3個實數加法就可完成。由上述算法編程得到的蝶形變換器經綜合后生成的原理圖如圖３所示。原理圖中clk是時鐘輸入引腳；X_re,X_im,Y_re,Y_im分別是復數X，Y的實部和虛部；Cin代表；cms和cps分別表示和 ;out1_re,out1_im,out2_re,out2_im代表蝶形變換后兩個輸出數據的實部和虛部。


      地址產生及控制單元對整個參與FFT運算的數據的存儲、讀寫時序進行控制，是 FFT 運算器的重要組成部分。地址產生及控制單元將要產生每一階運算單元輸入數據的讀寫地址、存儲器的讀寫、使能等控制信號，同時還要產生旋轉因子系數的讀出地址，將配對的數據和旋轉因子系數按序送入蝶形運算單元，從而實現每一階的蝶形運算。地址產生及控制單元的設計方法主要是利用有限狀態機進行設計。針對每一階運算單元的運算過程劃分成不同的狀態，不同的狀態下輸出不同的數據地址和控制信號。
    表1列出了計算一幀1024點FFT占用FPGA內部資源的情況。經后仿真時序分析，該激光告警系統在系統時鐘為50MHz的情況下,完成一幀1024點 FFT只需110μs,加上數據載入時間和數據讀取時間只需230μs,滿足實時處理的要求。從表中可以看出, FFT子模塊完成后, FPGA還有大量資源可以利用,因此剩余資源可用于采集模塊,從而在一塊芯片上完成多種功能,有效減少了激光告警機的體積。

在信號處理前直接對FPGA的輸入信號用Matlab仿真的頻譜如圖4，可見激光信號的波長峰值在523nm附近，數據在FPGA中進行FFT之后輸出的數據經過倒序后得到的頻譜結果如圖5，對比兩圖可知FPGA輸出與Matlab仿真結果基本相同，從而驗證了告警系統的正確性。

4 總結
本文介紹了為激光告警機探測目標激光的波長所開發的CCD相機信號采集與快速處理系統設備的設計。該系統利用FPGＡ實現對Atmel公司的AViiVA M2 CL型線陣CCD相機輸出數據的采集與處理，電路簡單，可靠性強，充分利用了FPGA支持多信號標準、支持流水作業工作模式、內設塊存儲器等特點。
本文作者創新點：在電路設計方面：擺脫了以往Cameralink接口型相機在與信號處理器進行通信時必須在相機和處理器之間加入電平轉換芯片的做法，充分利用了FPGA支持LVDS電平的優勢，從而減小了告警系統的電路體積和復雜度，在硬件方面提高了系統的可靠性。在程序設計方面：充分利用FPGA內部 RAM資源，多處用到FIFO存儲器，以流水作業為手段，縮短了系統響應時間。

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