</a>BLDC" title="BLDC">BLDC" title="BLDC">BLDC)馬達和交流感應電動機.本文介紹了LM3S818主要特性,方框圖, Stellaris® LM3S818 controlCARD模塊主要特性,框圖,電路圖和模塊元件布局圖.

The Stellaris® LM3S818 microcontroller is based on the ARM® Cortex™-M3 controller core operating at up to 50 MHz, with 64 kB flash and 8 kB SRAM. The LM3S818 also features real-time industrial connectivity, with an SSI / SPI controller, and 2 UARTs. The LM3S818 microcontroller also features advanced motion control features, including 6 motion-control PWM outputs with dead-band, a quadrature encoder input for precise position monitoring, and a fault protection input for low-latency shutdown. The microcontroller also features intelligent analog capability, including 1 analog comparators and 6 channels of highly accurate 10-bit analog-to-digital conversion - with the ability to sample at speeds of 1M samples per second.

LM3S818主要特性:

The LM3S818 microcontroller includes the following product features:
■ 32-Bit RISC Performance
– 32-bit ARM® Cortex™-M3 v7M architecture optimized for small-footprint embedded
Applications
– System timer (SysTick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism
– Thumb®-compatible Thumb-2-only instruction set processor core for high code density
– 50-MHz operation
– Hardware-division and single-cycle-multiplication
– Integrated Nested Vectored Interrupt Controller (NVIC) providing deterministic interrupt
handling
– 26 interrupts with eight priority levels
– Memory protection unit (MPU), providing a privileged mode for protected operating system functionality
– Unaligned data access, enabling data to be efficiently packed into memory
– Atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control
ARM® Cortex™-M3 Processor Core
– Compact core.
– Thumb-2 instruction set, delivering the high-performance expected of an ARM core in the memory size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications.
– Rapid application execution through Harvard architecture characterized by separate buses for instruction and data.
– Exceptional interrupt handling, by implementing the register manipulations required for handling an interrupt in hardware.
– Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining
– Memory protection unit (MPU) to provide a privileged mode of operation for complex
applications.
– Migration from the ARM7™ processor family for better performance and power efficiency.
– Full-featured debug solution
• Serial Wire JTAG Debug Port (SWJ-DP)
• Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
• Data Watchpoint and Trigger (DWT) unit for implementing watchpoints, trigger resources, and system profiling
• Instrumentation Trace Macrocell (ITM) for support of printf style debugging
• Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
– Optimized for single-cycle flash usage
– Three sleep modes with clock gating for low power
– Single-cycle multiply instruction and hardware divide
– Atomic operations
– ARM Thumb2 mixed 16-/32-bit instruction set
– 1.25 DMIPS/MHz
■ JTAG
– IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
– Four-bit Instruction Register (IR) chain for storing JTAG instructions
– IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST
– ARM additional instructions: APACC, DPACC and ABORT
Integrated ARM Serial Wire Debug (SWD)
■ Internal Memory
– 64 KB single-cycle flash
• User-managed flash block protection on a 2-KB block basis
• User-managed flash data programming
• User-defined and managed flash-protection block
– 8 KB single-cycle SRAM
■ GPIOs
– 0-30 GPIOs, depending on configuration
– 5-V-tolerant in input configuration
– Programmable control for GPIO interrupts
• Interrupt generation masking
• Edge-triggered on rising, falling, or both
• Level-sensitive on High or Low values
– Bit masking in both read and write operations through address lines
– Can initiate an ADC sample sequence
– Pins configured as digital inputs are Schmitt-triggered.
– Programmable control for GPIO pad configuration
• Weak pull-up or pull-down resistors
• 2-mA, 4-mA, and 8-mA pad drive for digital communication
• Slew rate control for the 8-mA drive
• Open drain enables
• Digital input enables
■ General-Purpose Timers
– Three General-Purpose Timer Modules (GPTM), each of which provides two 16-bit timers/counters. Each GPTM can be configured to operate independently:
• As a single 32-bit timer
• As one 32-bit Real-Time Clock (RTC) to event capture
• For Pulse Width Modulation (PWM)
• To trigger analog-to-digital conversions
– 32-bit Timer modes
• Programmable one-shot timer
• Programmable periodic timer
• Real-Time Clock when using an external 32.768-KHz clock as the input
• User-enabled stalling when the controller asserts CPU Halt flag during debug
• ADC event trigger
– 16-bit Timer modes
• General-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes
only)
• Programmable one-shot timer
• Programmable periodic timer
• User-enabled stalling when the controller asserts CPU Halt flag during debug
• ADC event trigger
– 16-bit Input Capture modes
• Input edge count capture
• Input edge time capture
– 16-bit PWM mode
• Simple PWM mode with software-programmable output inversion of the PWM signal
■ ARM FiRM-compliant Watchdog Timer
– 32-bit down counter with a programmable load register
– Separate watchdog clock with an enable
– Programmable interrupt generation logic with interrupt masking
– Lock register protection from runaway software
– Reset generation logic with an enable/disable
– User-enabled stalling when the controller asserts the CPU Halt flag during debug
■ ADC
– Six analog input channels
– Single-ended and differential-input configurations
On-chip internal temperature sensor
– Sample rate of one million samples/second
– Flexible, configurable analog-to-digital conversion
– Four programmable sample conversion sequences from one to eight entries long, with
corresponding conversion result FIFOs
– Flexible trigger control
• Controller (software)
• Timers
• Analog Comparators
• PWM
• GPIO
– Hardware averaging of up to 64 samples for improved accuracy
– Converter uses an internal 3-V reference
■ UART
– Two fully programmable 16C550-type UARTs
– Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
– Programmable baud-rate generator allowing speeds up to 3.125 Mbps
– Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
– FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
– Standard asynchronous communication bits for start, stop, and parity
– Line-break generation and detection
– Fully programmable serial interface characteristics
• 5, 6, 7, or 8 data bits
• Even, odd, stick, or no-parity bit generation/detection
• 1 or 2 stop bit generation
■ Synchronous Serial Interface (SSI)
– Master or slave operation
– Programmable clock bit rate and prescale
Separate transmit and receive FIFOs, 16 bits wide, 8 locations deep
– Programmable interface operation for Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces
– Programmable data frame size from 4 to 16 bits
– Internal loopback test mode for diagnostic/debug testing
■ Analog Comparators
– One integrated analog comparator
– Configurable for output to drive an output pin, generate an interrupt, or initiate an ADC sample sequence
– Compare external pin input to external pin input or to internal programmable voltage reference
– Compare a test voltage against any one of these voltages
• An individual external reference voltage
• A shared single external reference voltage
• A shared internal reference voltage
■ PWM
– Three PWM generator blocks, each with one 16-bit counter, two PWM comparators, a PWM signal generator, a dead-band generator, and an interrupt/ADC-trigger selector
– One fault input in hardware to promote low-latency shutdown
– One 16-bit counter
• Runs in Down or Up/Down mode
• Output frequency controlled by a 16-bit load value
• Load value updates can be synchronized
• Produces output signals at zero and load value
– Two PWM comparators
• Comparator value updates can be synchronized
• Produces output signals on match
– PWM generator
• Output PWM signal is constructed based on actions taken as a result of the counter and
PWM comparator output signals
• Produces two independent PWM signals
Dead-band generator
• Produces two PWM signals with programmable dead-band delays suitable for driving a
half-H bridge
• Can be bypassed, leaving input PWM signals unmodified
– Flexible output control block with PWM output enable of each PWM signal
• PWM output enable of each PWM signal
• Optional output inversion of each PWM signal (polarity control)
• Optional fault handling for each PWM signal
• Synchronization of timers in the PWM generator blocks
• Synchronization of timer/comparator updates across the PWM generator blocks
• Interrupt status summary of the PWM generator blocks
– Can initiate an ADC sample sequence
■ QEI
– Position integrator that tracks the encoder position
– Velocity capture using built-in timer
– The input frequency of the QEI inputs may be as high as 1/4 of the processor frequency (for example, 12.5 MHz for a 50-MHz system)
– Interrupt generation on:
• Index pulse
• Velocity-timer expiration
• Direction change
• Quadrature error detection
■ Power
– On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable from 2.25 V to 2.75 V
– Low-power options on controller: Sleep and Deep-sleep modes
– Low-power options for peripherals: software controls shutdown of individual peripherals
– User-enabled LDO unregulated voltage detection and automatic reset
– 3.3-V supply brown-out detection and reporting via interrupt or reset
■ Flexible Reset Sources
– Power-on reset (POR)
– Reset pin assertion
– Brown-out (BOR) detector alerts to system power drops
– Software reset
– Watchdog timer reset
– Internal low drop-out (LDO) regulator output goes unregulated
■ Industrial and extended temperature 48-pin RoHS-compliant LQFP package
■ Industrial and extended temperature 48-pin RoHS-compliant QFN package

LM3S818目標應用:

■ Factory automation and control

■ Industrial control power devices

■ Building and home automation

■ Stepper motors

■ Brushless DC motors

■ AC induction motors

圖1. Stellaris LM3S818 MCU方框圖

圖2. LM3S818控制器系統級框圖

Stellaris® LM3S818 controlCARD模塊

The Stellaris® LM3S818 controlCARD module is a DIMM form-factor module that can be used standalone or with a range of baseboards to accelerate evaluation and development.

Texas Instruments offers a range of controlCARD baseboards for motor and power-control application. In most cases. these are available as complete kits that include a controlCARD module and a baseboard. The Stellaris MDL-LM3S818CNCD is part of a controlCARD lineup that includes cards for C2000 and MSP430 devices.

圖3. LM3S818 controlCARD三相BLDC馬達模塊外形圖

LM3S818 controlCARD模塊包括:

The LM3S818 controlCARD module kit comes with the following:

?? MDL-LM3S818CNCD controlCARD module
– On board Stellaris In-Circuit Debug Interface
?? Cables/Accessories
– USB-miniB to USB-A plug cable (for debug and serial communication)
– 1/2-inch blue jumper wires (for bridging power)
?? Development Kit CD containing:
– For the controlCARD module in standalone use:
• Complete documentation
• StellarisWare® Peripheral Driver Library and example source code
– For the controlCARD module when used with a supported baseboard:
• Source-code and binaries
• Documentation specific to each supported baseboard
• CrossHairs control GUI Windows application
??Tools CD(s)
Texas Instruments’ Code Composer Studio™ IDE
Stellaris MDL-LM3S818CNCD controlCARD模塊主要特性:
The Stellaris MDL-LM3S818CNCD controlCARD module includes the following features:
?? LM3S818IQN50 Stellaris microcontroller
– 32-bit ARM® Cortex™-M3 core
– 50 MHz max speed
– 64 KB Flash, 8 KB RAM
?? DIMM form-factor
?? GPIO signals available on DIMM edge-connector
?? User LED
?? Debug
– Stellaris In-Circuit Debug Interface (ICDI)
Isolated to 560 V working-voltage using Texas’Instruments’ digital isolators


圖4. LM3S818 controlCARD模塊方框圖

圖5. LM3S818 controlCARD模塊電路圖(1)

圖6. LM3S818 controlCARD模塊電路圖(2)


圖7. LM3S818 controlCARD模塊元件布局圖:上圖:頂層,下圖:底層
詳情請見:
http://www.ti.com/lit/ds/symlink/lm3s818.pdf
和
http://www.ti.com/lit/ug/spmu275/spmu275.pdf