中圖分類號：TN402
文獻標志碼：A
DOI: 10.16157/j.issn.0258-7998.223036
中文引用格式： 袁金煥，王艷玲，殷麗麗，等. 基于芯片封裝的微系統模塊PDN設計優化[J]. 電子技術應用，2023，49(2)：32-38.
英文引用格式： Yuan Jinhuan，Wang Yanling，Yin Lili，et al. PDN design optimization of micro-system based on package[J]. Application of Electronic Technique，2023，49(2)：32-38.

PDN design optimization of micro-system based on package

Abstract： As the power supply of IC chips tends to be low-voltage and high-current, the design of the Power Delivery Network(PDN) of the micro-system module is becoming more and more important, based on 2.5D Through-Silicon-Via(TSV), inverted solder, High Temperature Co-fired Ceramics(HTCC),3D stacking, etc. Chip currents generate output noise through PDN interconnects, which must provide a better signal return path with low-impedance to keep the supply voltage between chip pads constant within a small tolerance range, usually 5% or less. Based on Chip Package System(CPS), the paper proposes a design and optimization method for the micro-system module PDN based on the three-level synergy of TSV silicon substrate, HTCC cases and PCB. This paper expounds the DC design and AC impedance design respectively, and using the Chip Power Model(CPM) combined with the time domain analysis, realizes the low impedance design of the power ripple on PDN.

Key words : TSV；HTCC；micro-system；PDN；package