基于PG網絡的全流程優化在高性能CPU內核中的應用
2023年電子技術應用第8期
姜姝，楊超，吳馳
（上海云豹創芯智能科技有限公司，上海 201210）
摘要： 隨著高性能計算芯片的集成度不斷提高以及工藝的進步， 金屬連線的寬度越來越窄，芯片電源網絡上電阻增加和高密度的邏輯門單元同時有邏輯翻轉動作時會在電源網絡上產生電壓降（IR Drop），導致芯片產生時序問題，甚至可能發生邏輯門的功能故障。
中圖分類號：TN402 文獻標志碼：A DOI: 10.16157/j.issn.0258-7998.239807
中文引用格式： 姜姝，楊超，吳馳. 基于PG網絡的全流程優化在高性能CPU內核中的應用[J]. 電子技術應用，2023，49(8)：36-41.
英文引用格式： Jiang Shu，Yang Chao，Wu Chi. Application of fully automated optimization based on PG network in high performance CPU core[J]. Application of Electronic Technique，2023，49(8)：36-41.
中文引用格式： 姜姝，楊超，吳馳. 基于PG網絡的全流程優化在高性能CPU內核中的應用[J]. 電子技術應用，2023，49(8)：36-41.
英文引用格式： Jiang Shu，Yang Chao，Wu Chi. Application of fully automated optimization based on PG network in high performance CPU core[J]. Application of Electronic Technique，2023，49(8)：36-41.
Application of fully automated optimization based on PG network in high performance CPU core
Jiang Shu，Yang Chao，Wu Chi
(Jaguar Microsystems， Shanghai 201210， China)
Abstract： With the continuous improvement of the integration of high-performance computing chips and the advancement of technology, the width of metal wires is getting narrower and narrower, and the voltage drop (IR drop) will occur on the power network when the resistance on the chip power network increases and the high-density logic gate unit has a logic flip action at the same time, resulting in timing problems in the chip, and even the functional failure of the logic gate may occur. Based on the flash PG flow of the Cadence implementation tool Innovus, this paper completes the comprehensive implementation and rapid iteration of the PG network, and uses auto reinforce PG and trim PG to realize the trade-off between the voltage drop and timing of the high-performance CPU core from two aspects, and completes the whole process optimization of the PG network from floorplan to PR (Placement and Route) stage. The results show that under the premise of the same machine resources, flash PG flow can increase the speed of powerplan up to 10 times the original, especially in the design of the top level, which can effectively save the exploration time of PG mesh in the early stage of design. Auto reinforce PG and trim PG repair 66% of the dynamic IR drop violations by reinforcing the PG of the weak IR area and trimming the redundant PG respectively, and at the same time provide more winding resources for the design to achieve the purpose of not deteriorating the timing and DRC (Design Rule Check).
Key words : chip design；flasg PG；IR drop fixing
0 引言
隨著高性能計算芯片的集成度不斷提高以及工藝的進步，加上邏輯電路與電源網絡的復雜程度也越來越高，芯片中某些區域會出現局部電流較大的現象，使得所在區域電壓降 (IR Drop)增大，導致邏輯單元上的實際工作電壓低于理想工作電壓，導致芯片產生時序問題，甚至可能發生邏輯門的功能故障[1-4]。本文基于Cadence實現工具Innovus的flash PG flow完成對于PG 網絡的綜合實現與快速迭代，并利用 auto reinforce PG和trim PG從兩方面實現了對高性能CPU核的電壓降與時序之間的trade-off，完成從布圖規劃(floorplan)階段到PR(Placement and Route)階段針對PG網絡的流程優化。
本文詳細內容請下載：http://www.cowatch.cn/resource/share/2000005478
作者信息：
姜姝，楊超，吳馳
（上海云豹創芯智能科技有限公司，上海 201210）
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