探索分布式仿真方法加速Chiplet系統級驗證
電子技術應用
徐加山1，何金鑫1，劉紅云1，徐志磊2
1.深圳市中興微電子技術有限公司；2.上?？请娮涌萍加邢薰?/div>
摘要： 隨著人工智能（AI）和高性能計算領域對芯片算力需求的增長，Chiplet方案正日益受到行業重視。然而Multi-Die系統復雜性和規模的擴大導致仿真消耗服務器資源大、驗證交付周期延長等。為解決這些問題，分析了傳統的三步法和Socket驗證方法，重點探索了Cadence分布式仿真方案，基于某實際Chiplet項目將系統級仿真任務分解成多個子Die并行執行的仿真實例，從服務器內存、跨服務器通信延遲、同步時間精準調控、信號連接開始時間及信號連接數量等多個方面探索了分布式仿真提效的措施，實現了超大規模Chiplet系統級RTL仿真和回歸效率提升。
中圖分類號：TN407 文獻標志碼：A DOI: 10.16157/j.issn.0258-7998.250807
中文引用格式： 徐加山，何金鑫，劉紅云，等. 探索分布式仿真方法加速Chiplet系統級驗證[J]. 電子技術應用，2025，51(8)：35-39.
英文引用格式： Xu Jiashan，He Jinxin，Liu Hongyun，et al. Research on accelerating chiplet system level verification with distributed simulation technology[J]. Application of Electronic Technique，2025，51(8)：35-39.
中文引用格式： 徐加山，何金鑫，劉紅云，等. 探索分布式仿真方法加速Chiplet系統級驗證[J]. 電子技術應用，2025，51(8)：35-39.
英文引用格式： Xu Jiashan，He Jinxin，Liu Hongyun，et al. Research on accelerating chiplet system level verification with distributed simulation technology[J]. Application of Electronic Technique，2025，51(8)：35-39.
Research on accelerating chiplet system level verification with distributed simulation technology
Xu Jiashan1，He Jinxin1，Liu Hongyun1，Xu Zhilei2
1.Sanechips Technology Co.，Ltd.；2.Cadence Design Systems，Inc.
Abstract： With the increasing demand for chip computing power in the fields of AI and high-performance computing, the chiplet solution is attracting more and more attention in the industry. However, the expansion of complexity and scale in multi-Die systems leads to issues such as high server resource consumption during simulation and extended verification delivery cycles. To solve these problems, this paper analyzes the traditional three-step method and socket verification method, and focuses on the Cadence distributed simulation solution. Based on an actual chiplet project, this paper breaks down system-level simulation tasks into multiple sub-Dies for parallel execution, and explores distributed simulation measures to improve efficiency from multiple aspects, such as server memory, cross-server communication delay, precise synchronization time adjustment, signal connection start time, and signal connection quantity. This achieves ultra-large-scale chiplet system-level RTL simulation and improves regression efficiency.
Key words : chiplet；system level validation；distributed simulation technology
引言
隨著高性能計算、人工智能及自動駕駛等帶寬密集型應用的快速發展，傳統大的單芯片面臨良率風險，推動著系統架構正從傳統單芯片向多芯片集成方向演進，但這也導致系統級驗證難度顯著增加?，F有驗證方法在應對Chiplet系統級仿真時存在運行效率低下、驗證交付周期長等問題。因此，本文探索了基于分布式仿真的驗證方案，通過構建并行化仿真任務調度機制和資源分配策略，實現多芯片協同驗證的效率提升。
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http://www.cowatch.cn/resource/share/2000006626
作者信息：
徐加山1，何金鑫1，劉紅云1，徐志磊2
（1.深圳市中興微電子技術有限公司，江蘇 南京 210012；2.上?？请娮涌萍加邢薰?，上海 200235）
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